Display panel

ABSTRACT

A display panel is provided. The display panel includes a base substrate, a plurality of subpixels. A respective subpixel includes a respective light emitting element and a respective pixel driving circuit. The respective pixel driving circuit includes a third transistor; and a storage capacitor including a first capacitor electrode in a first conductive layer and a second capacitor electrode in a second conductor layer. The second conductive layer is on a side of the first conductive layer away from the base substrate. The second capacitor electrode includes an extension extending away from an electrode main body of the second capacitor electrode. An orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor of the respective pixel driving circuit on the base substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.17/764,479, filed Jun. 25, 2021, which a national stage applicationunder 35 U.S.C. § 371 of International Application No.PCT/CN2021/102249, filed Jun. 25, 2021. Each of the forgoingapplications is herein incorporated by reference in its entirety for allpurposes.

TECHNICAL FIELD

The present invention relates to display technology, more particularly,to a display panel.

BACKGROUND

Organic Light Emitting Diode (OLED) display is one of the hotspots inthe field of flat panel display research today. Unlike Thin FilmTransistor-Liquid Crystal Display (TFT-LCD), which uses a stable voltageto control brightness, OLED is driven by a driving current required tobe kept constant to control illumination. The OLED display panelincludes a plurality of pixel units configured with pixel-drivingcircuits arranged in multiple rows and columns. Each pixel-drivingcircuit includes a driving transistor having a gate terminal connectedto one gate line per row and a drain terminal connected to one data lineper column. When the row in which the pixel unit is gated is turned on,the switching transistor connected to the driving transistor is turnedon, and the data voltage is applied from the data line to the drivingtransistor via the switching transistor, so that the driving transistoroutputs a current corresponding to the data voltage to an OLED device.The OLED device is driven to emit light of a corresponding brightness.

SUMMARY

In one aspect, the present disclosure provides a display panel,comprising a base substrate, a plurality of subpixels, a respectivesubpixel comprising a respective light emitting element and a respectivepixel driving circuit; wherein the respective pixel driving circuitcomprises a third transistor; and a storage capacitor comprising a firstcapacitor electrode in a first conductive layer and a second capacitorelectrode in a second conductor layer; wherein the second conductivelayer is on a side of the first conductive layer away from the basesubstrate; the second capacitor electrode comprises an extensionextending away from an electrode main body of the second capacitorelectrode; and an orthographic projection of the extension on the basesubstrate at least partially overlaps with an orthographic projection ofan active layer of the third transistor of the respective pixel drivingcircuit on the base substrate.

Optionally, the third transistor comprises a first gate electrode and asecond gate electrode; an orthographic projection of the first gateelectrode on the base substrate overlaps with an orthographic projectionof a first channel part of the active layer of the third transistor onthe base substrate; an orthographic projection of the second gateelectrode on the base substrate overlaps with an orthographic projectionof a second channel part of the active layer of the third transistor onthe base substrate; the active layer of the third transistor furthercomprises a portion connecting the first channel part and the secondchannel part; and the orthographic projection of the extension on a basesubstrate at least partially overlaps with an orthographic projection ofthe portion connecting the first channel part and the second channelpart on the base substrate.

Optionally, the display panel further comprises a first signal linelayer on a side of the storage capacitor away from the base substrate;wherein multiple second capacitor electrodes respectively from multiplepixel driving circuits are sequentially connected to each other along afirst direction; the first signal line layer comprises a plurality offirst high voltage signal lines respectively along a first direction;and a respective one of the plurality of first high voltage signal linesis connected to the second capacitor electrode.

Optionally, the extension comprises a first extension part along asecond direction and a second extension part along a first direction;the first extension part connects the second extension part with theelectrode main body of the second capacitor electrode; and anorthographic projection of the second extension part on the basesubstrate at least partially overlaps with the orthographic projectionof the active layer of the third transistor of the respective pixeldriving circuit on the base substrate.

Optionally, the second extension part comprises a shielding portion anda non-shielding portion; an orthographic projection of the shieldingportion on the base substrate at least partially overlaps with theorthographic projection of the active layer of the third transistor ofthe respective pixel driving circuit on the base substrate; anorthographic projection of the non-shielding portion on the basesubstrate is non-overlapping with the orthographic projection of theactive layer of the third transistor of the respective pixel drivingcircuit on the base substrate; and a line width of the shielding portionis greater than a line width of the non-shielding portion.

Optionally, the respective pixel driving circuit further comprises adriving transistor, and a node connecting line connecting a drainelectrode of the third transistor with a gate electrode of the drivingtransistor; wherein the drain electrode of the third transistor isconnected to the gate electrode of the driving transistor; a sourceelectrode of the third transistor is connected to a drain electrode ofthe driving transistor; and an orthographic projection of the firstextension part on a line extending along the second direction at leastpartially overlaps with an orthographic projection of the nodeconnecting line on the line.

Optionally, the display panel further comprises a plurality of datalines; wherein the first extension part is between the node connectingline and a respective data line of the plurality of data lines.

Optionally, the display panel further comprises a plurality of gatelines; wherein a respective gate line of the plurality of gate linescomprises a plurality of metal blocks spaced apart from each other in afirst conductive layer, and a metal line along a first direction in afirst signal line layer, the metal line along the first direction beingconnected to the plurality of metal blocks through vias, respectively.

Optionally, a respective metal block of the plurality of metal blockshas a L shape; an orthographic projection of a first channel part of theactive layer of the third transistor on the base substrate overlaps withan orthographic projection of a first metal portion of the respectivemetal block of the plurality of metal blocks on the base substrate; anorthographic projection of a second channel part of the active layer ofthe third transistor on the base substrate overlaps with an orthographicprojection of a second metal portion of the respective metal block ofthe plurality of metal blocks on the base substrate; and the first metalportion and the second metal portion are a first gate electrode and asecond gate electrode of the third transistor.

Optionally, the display panel further comprises a plurality of firstreset signal lines respectively along a first direction in asemiconductor material layer; and a plurality of second reset signallines respectively along a second direction in a second signal linelayer; wherein the plurality of first reset signal lines respectivelycross over the plurality of second reset signal lines; a respective oneof the plurality of first reset signal lines is connected to at leastmultiple ones of the plurality of second reset signal lines throughvias; and a respective one of the plurality of second reset signal linesis connected to at least multiple ones of the plurality of first resetsignal lines through vias.

Optionally, the display panel further comprises a plurality of secondlow voltage signal lines respectively along a second direction in asecond signal line layer; wherein the plurality of second low voltagesignal lines are electrically connected to a cathode of a light emittingelement.

Optionally, the display panel further comprises a plurality of firsthigh voltage signal lines respectively extending along the firstdirection in a first signal line layer; a plurality of second highvoltage signal lines respectively extending along a second direction ina second signal line layer; wherein the plurality of first high voltagesignal lines respectively cross over the plurality of second highvoltage signal lines; a respective one of the plurality of first highvoltage signal lines is connected to at least multiple ones of theplurality of second high voltage signal lines through vias; and arespective one of the plurality of second high voltage signal lines isconnected to at least multiple ones of the plurality of first highvoltage signal lines through vias.

Optionally, a respective one of the plurality of first high voltagesignal lines comprises a main body extending along a first direction; afirst protrusion protruding away from the main body along a seconddirection, and a second protrusion protruding away from the firstprotrusion along the second direction; wherein the second protrusionconnects to the main body through the first protrusion; and the secondprotrusion is a portion of the respective one of the plurality of secondhigh voltage signal line where the respective one of the plurality ofsecond high voltage signal line is connected to a respective one of theplurality of first high voltage signal lines through one or more vias.

Optionally, the respective pixel driving circuit further comprises adriving transistor, and a node connecting line connecting a drainelectrode of the third transistor with a gate electrode of the drivingtransistor; wherein the drain electrode of the third transistor isconnected to the gate electrode of the driving transistor; a sourceelectrode of the third transistor is connected to a drain electrode ofthe driving transistor; and an orthographic projection of the respectiveone of the plurality of second high voltage signal lines on the basesubstrate covers an orthographic projection of the node connecting lineon the base substrate.

Optionally, an orthographic projection of the respective one of theplurality of second high voltage signal lines on the base substrate atleast partially overlaps with an orthographic projection of at least onegate electrode of the third transistor on the base substrate.

Optionally, the display panel comprises a plurality of light emittingelements; and an interconnected first voltage supply network configuredto provide a first voltage signal to cathodes of the plurality of lightemitting elements; wherein the interconnected first voltage supplynetwork comprises signal lines in a display area of the display panel,the display area being at least partially surrounded by a peripheralarea; the signal lines comprise a plurality of first signal lines in afirst signal line layer and a plurality of second signal lines in asecond signal line layer; the display panel further comprises aplanarization layer between the first signal line layer and the secondsignal line layer; and the plurality of first signal lines areelectrically connected to the plurality of second signal lines.

Optionally, the interconnected first voltage supply network comprises aplurality of first-first voltage signal lines respectively along a firstdirection; and a plurality of second-first voltage signal linesrespectively along a second direction; wherein the plurality offirst-first voltage signal lines respectively cross over the pluralityof second-first voltage signal lines.

Optionally, the interconnected first voltage supply network comprises afirst sub-network formed by the plurality of first-first voltage signallines and a second sub-network formed by the plurality of second-firstvoltage signal lines.

Optionally, a respective one of the plurality of first-first voltagesignal lines is connected to at least multiple ones of the plurality ofsecond-first voltage signal lines; and a respective one of the pluralityof second-first voltage signal lines is connected to at least multipleones of the plurality of first-first voltage signal lines.

Optionally, the plurality of first-first voltage signal lines and theplurality of second-first voltage signal lines interconnect throughfirst vias respectively extending through the planarization layer, atleast some of the first vias being in the display area; a respective oneof the plurality of first-first voltage signal lines is connected to atleast multiple ones of the plurality of second-first voltage signallines respectively through multiple first vias extending through theplanarization layer; and a respective one of the plurality ofsecond-first voltage signal lines is connected to at least multiple onesof the plurality of first-first voltage signal lines respectivelythrough multiple first vias extending through the planarization layer.

In another aspect, the present disclosure provides a display panel,comprising a plurality of subpixels, a respective subpixel comprising arespective light emitting element and a respective pixel drivingcircuit; wherein the display panel comprises a plurality of lightemitting elements; and an interconnected first voltage supply networkconfigured to provide a first voltage signal to cathodes of theplurality of light emitting elements; wherein the interconnected firstvoltage supply network comprises signal lines in a display area of thedisplay panel, the display area being at least partially surrounded by aperipheral area; the signal lines comprise a plurality of first signallines in a first signal line layer and a plurality of second signallines in a second signal line layer; the display panel further comprisesa planarization layer between the first signal line layer and the secondsignal line layer; and the plurality of first signal lines areelectrically connected to the plurality of second signal lines.

Optionally, the interconnected first voltage supply network comprises aplurality of first-first voltage signal lines respectively along a firstdirection; and a plurality of second-first voltage signal linesrespectively along a second direction; wherein the plurality offirst-first voltage signal lines respectively cross over the pluralityof second-first voltage signal lines.

Optionally, the interconnected first voltage supply network comprises afirst sub-network formed by the plurality of first-first voltage signallines and a second sub-network formed by the plurality of second-firstvoltage signal lines.

Optionally, a respective one of the plurality of first-first voltagesignal lines is connected to at least multiple ones of the plurality ofsecond-first voltage signal lines; and a respective one of the pluralityof second-first voltage signal lines is connected to at least multipleones of the plurality of first-first voltage signal lines.

Optionally, the plurality of first-first voltage signal lines and theplurality of second-first voltage signal lines interconnect throughfirst vias respectively extending through the planarization layer, atleast some of the first vias being in the display area; a respective oneof the plurality of first-first voltage signal lines is connected to atleast multiple ones of the plurality of second-first voltage signallines respectively through multiple first vias extending through theplanarization layer; and a respective one of the plurality ofsecond-first voltage signal lines is connected to at least multiple onesof the plurality of first-first voltage signal lines respectivelythrough multiple first vias extending through the planarization layer.

Optionally, the display panel further comprises a gate-on-array circuitin a peripheral area of the display panel; wherein the interconnectedfirst voltage supply network comprises a first peripheral first voltageline in the peripheral area on a first side of the display panel; and anorthographic projection of the first peripheral first voltage line on abase substrate at least partially overlaps with an orthographicprojection of the gate-on-array circuit on the base substrate.

Optionally, the display panel further comprises an anode metal layer ona side of the first peripheral first voltage line away from thegate-on-array circuit; and a cathode layer on a side of the anode metallayer away from the first peripheral first voltage line; wherein thecathode layer is connected to the anode metal layer through one or morefirst peripheral vias in the peripheral area and extending through athird planarization layer, the anode metal layer is connected to thefirst peripheral first voltage line through one or more secondperipheral vias in the peripheral area and extending through a secondplanarization layer, thereby providing the first voltage signal to thecathodes of the plurality of light emitting elements; the one or morefirst peripheral vias connecting the cathode layer and the anode metallayer, and the one or more second peripheral vias connecting the anodemetal layer and the interconnected first voltage supply network arelimited in the peripheral area, and absent in the display area; and thefirst peripheral first voltage line and the anode metal layer connectedto the first peripheral first voltage line respectively partiallysurround a display area.

Optionally, the display panel further comprises an interconnected resetsignal supply network configured to provide a reset signal to aplurality of pixel driving circuits; wherein the interconnected resetsignal supply network comprises signal lines in a display area of thedisplay panel.

Optionally, the interconnected reset signal supply network comprises aplurality of first reset signal lines respectively along a firstdirection; and a plurality of second reset signal lines respectivelyalong a second direction; wherein the plurality of first reset signallines respectively cross over the plurality of second reset signallines.

Optionally, a respective one of the plurality of first reset signallines is connected to at least multiple ones of the plurality of secondreset signal lines; and a respective one of the plurality of secondreset signal lines is connected to at least multiple ones of theplurality of first reset signal lines.

Optionally, a minimal distance between a respective second reset signalline of the plurality of second reset signal lines and a respectivesecond-first voltage signal line of the plurality of second-firstvoltage signal lines that is most adjacent to the respective secondreset signal line is less than a minimal distance between the respectivesecond reset signal line and a respective data line of a plurality ofdata line that is most adjacent to the respective second reset signalline.

Optionally, a total of three data lines and a total of one second-firstvoltage signal line are between two most adjacent second reset signallines of the plurality of second reset signal lines.

Optionally, the display panel comprises a base substrate; asemiconductor material layer on the base substrate; a planarizationlayer on a side of the semiconductor material layer away from the basesubstrate; a second signal line layer on a side of the planarizationlayer away from the semiconductor material layer; wherein the displaypanel further comprises an interconnected reset signal supply networkconfigured to provide a reset signal to a plurality of pixel drivingcircuits; the interconnected reset signal supply network comprises aplurality of first reset signal lines respectively along a firstdirection and a plurality of second reset signal lines respectivelyalong a second direction; and the semiconductor material layer comprisesthe plurality of first reset signal lines, and the second signal linelayer comprises the plurality of second reset signal lines.

Optionally, the plurality of first reset signal lines and the pluralityof second reset signal lines interconnect through second viasrespectively extending through at least the planarization layer; whereinthe display panel further comprises a gate insulating layer on a side ofthe semiconductor material layer away from the base substrate; aninsulating layer on a side of the gate insulating layer away from thesemiconductor material layer; and an inter-layer dielectric layer a sideof the insulating layer away from the gate insulating layer; wherein theplanarization layer is on a side of the inter-layer dielectric layeraway from the insulating layer; and the plurality of first reset signallines and the plurality of second reset signal lines interconnectthrough second vias, a respective second via extending through theplanarization layer, the inter-layer dielectric layer, the insulatinglayer, and the gate insulating layer.

Optionally, a respective one of the plurality of first reset signallines is connected to at least multiple ones of the plurality of secondreset signal lines respectively through multiple second vias extendingthrough at least the planarization layer; and a respective one of theplurality of second reset signal lines is connected to at least multipleones of the plurality of first reset signal lines respectively throughmultiple second vias extending through at least the planarization layer.

Optionally, the plurality of first reset signal lines comprise asemiconductor material; the plurality of second reset signal linescomprise a metallic material; and the plurality of first reset signallines and at least active layers of a plurality of thin film transistorsare in the semiconductor material layer, and comprise a samesemiconductor material.

Optionally, the display panel further comprises an interconnected secondvoltage supply network configured to provide a second voltage signal toa plurality of pixel driving circuits; wherein the interconnected secondvoltage supply network comprises a plurality of first-second voltagesignal lines respectively along a first direction; and a plurality ofsecond-second voltage signal lines respectively along a seconddirection; wherein the plurality of first-second voltage signal linesrespectively cross over the plurality of second-second voltage signallines.

Optionally, a respective one of the plurality of first-second voltagesignal lines is connected to at least multiple ones of the plurality ofsecond-second voltage signal lines; and a respective one of theplurality of second-second voltage signal lines is connected to at leastmultiple ones of the plurality of first-second voltage signal lines.

Optionally, the display panel comprises a base substrate; a first signalline layer on the base substrate; a planarization layer on a side of thefirst signal line layer away from the base substrate; a second signalline layer on a side of the planarization layer away from the firstsignal line layer; wherein the interconnected second voltage supplynetwork comprises a plurality of first-second voltage signal linesrespectively along a first direction and a plurality of second-secondvoltage signal lines respectively along a second direction; wherein thefirst signal line layer comprises the plurality of first-second voltagesignal lines, and the second signal line layer comprises the pluralityof second-second voltage signal lines.

Optionally, the plurality of first-second voltage signal lines and theplurality of second-second voltage signal lines interconnect throughthird vias respectively extending through the planarization layer; arespective one of the plurality of first-second voltage signal lines isconnected to at least multiple ones of the plurality of second-secondvoltage signal lines respectively through multiple third vias extendingthrough the planarization layer; and a respective one of the pluralityof second-second voltage signal lines is connected to at least multipleones of the plurality of first-second voltage signal lines respectivelythrough multiple third vias extending through the planarization layer.

Optionally, a respective one of a plurality of first-second voltagesignal lines comprises a main body extending along a first direction; afirst protrusion protruding away from the main body along a seconddirection, and a second protrusion protruding away from the firstprotrusion along the second direction; wherein the second protrusionconnects to the main body through the first protrusion; the firstprotrusion is a portion of the respective one of the plurality offirst-second voltage signal lines where the respective one of aplurality of first-second voltage signal lines connects to a secondcapacitor electrode; and the second protrusion is a portion of therespective one of the plurality of first-second voltage signal lineswhere the respective one of the plurality of first-second voltage signallines connects to a source electrode of a fourth transistor of arespective pixel driving circuit, a drain electrode of the fourthtransistor being connected to a source electrode of a drivingtransistor.

Optionally, the display panel further comprises a plurality ofsecond-second voltage signal lines at least partially in the displayarea; and a peripheral second voltage signal line in the peripheral areaon a second side of the display panel; wherein the interconnected firstvoltage supply network comprises a plurality of first-first voltagesignal lines and a plurality of second-first voltage signal lines atleast partially in the display area; and a second peripheral firstvoltage signal line and a third peripheral first voltage signal line inthe peripheral area on the second side of the display panel; wherein oneor more of the plurality of second-second voltage signal lines areconnected to the peripheral second voltage signal line; one or more ofthe plurality of second-first voltage signal lines are connected to thesecond peripheral first voltage signal line; the second peripheral firstvoltage signal line and the third peripheral first voltage signal lineare connected to each other through a plurality of bridges; theplurality of first-first voltage signal lines, the peripheral secondvoltage signal line, and the plurality of bridges are in a first signalline layer; the plurality of second-second voltage signal lines, thesecond peripheral first voltage signal line are in a second signal linelayer; and the third peripheral first voltage signal line comprise afirst sub-layer in the first signal line layer and a second sub-layer inthe second signal line layer.

Optionally, the display panel further comprises a plurality of gatelines; wherein a respective gate line of the plurality of gate linescomprises a plurality of metal blocks spaced apart from each other in afirst conductive layer, and a metal line along a first direction in thefirst signal line layer, the signal line along the first direction beingconnected to the plurality of metal blocks, respectively.

Optionally, the display panel further comprises a plurality of firstreset control signal line and a plurality of second reset control signallines; a respective first reset control signal line and a respectivesecond reset control signal line are respectively configured to reset agate electrode of a driving transistor and an anode of a respectivelight emitting element; the respective first reset control signal linecomprises a plurality of first metal blocks spaced apart from each otherin a first conductive layer, and a first metal line along a firstdirection in the first signal line layer, the first metal line along thefirst direction being connected to the plurality of first metal blocks,respectively; and the respective second reset control signal linecomprises a plurality of second metal blocks spaced apart from eachother in the first conductive layer, and a second metal line along thefirst direction in the first signal line layer, the second metal linealong the first direction being connected to the plurality of secondmetal blocks, respectively.

Optionally, a respective first-first voltage signal line of a pluralityof first-first voltage signal lines comprises a first linear portion, asecond linear portion, and a connecting portion connecting the firstlinear portion and the second linear portion; a virtual extension of thefirst linear portion crosses over the plurality of first metal blocks ofthe respective first reset control signal line; and an orthographicprojection of the second linear portion on a base substrate is spacedapart from orthographic projections the plurality of first metal blockson the base substrate.

Optionally, the display panel further comprises a second capacitorelectrode of a storage capacitor in a second conductive layer; thesecond capacitor electrode comprises an extension extending away from anelectrode main body of the second capacitor electrode; an orthographicprojection of the extension on a base substrate at least partiallyoverlaps with an orthographic projection of an active layer of a thirdtransistor of the respective pixel driving circuit on the basesubstrate; and a portion of the extension is between a first node of therespective pixel driving circuit and a respective data line, configuredto prevent interference from signals passing through the respective dataline to the first node, the first node being configured to have a samevoltage level as a gate electrode of a driving transistor.

BRIEF DESCRIPTION OF THE FIGURES

The following drawings are merely examples for illustrative purposesaccording to various disclosed embodiments and are not intended to limitthe scope of the present invention.

FIG. 1 is a schematic diagram illustrating the structure of a displaypanel in some embodiments according to the present disclosure.

FIG. 2 is a plan view of a display panel in some embodiments accordingto the present disclosure.

FIG. 3 is a circuit diagram illustrating the structure of a pixeldriving circuit in some embodiments according to the present disclosure.

FIG. 4A is a diagram illustrating the structure of three pixel drivingcircuits for driving light emission of three light emitting elements ofa display panel in some embodiments according to the present disclosure.

FIG. 4B is a diagram illustrating the structure of a semiconductormaterial layer in a display panel depicted in FIG. 4A.

FIG. 4C is a diagram illustrating the structure of a first conductivelayer in a display panel depicted in FIG. 4A.

FIG. 4D is a diagram illustrating the structure of a second conductivelayer in a display panel depicted in FIG. 4A.

FIG. 4E is a diagram illustrating the structure of a first signal linelayer in a display panel depicted in FIG. 4A.

FIG. 4F is a diagram illustrating the structure of a second signal linelayer in a display panel depicted in FIG. 4A.

FIG. 4G is a diagram illustrating the structure of a respective one of aplurality of first high voltage signal lines in some embodimentsaccording to the present disclosure.

FIG. 4H is a diagram illustrating the layout of anodes of light emittingelements with respect to pixel driving circuits of a display panel insome embodiments according to the present disclosure.

FIG. 4I is a diagram illustrating the structure of anodes, a firstsignal line layer, and a second signal line layer in a display panel insome embodiments according to the present disclosure.

FIG. 4J is a diagram illustrating a relative position between arespective one of a plurality of first low voltage signal lines and aplurality of first metal blocks of a respective first reset controlsignal line in some embodiments according to the present disclosure.

FIG. 5A is a cross-sectional view along an A-A′ line in FIG. 4A.

FIG. 5B is a cross-sectional view along a B-B′ line in FIG. 4A.

FIG. 5C is a cross-sectional view along a C-C′ line in FIG. 4A.

FIG. 5D is a cross-sectional view along a D-D′ line in FIG. 4A.

FIG. 5E is a cross-sectional view along a E-E′ line in FIG. 4A.

FIG. 6A is a diagram illustrating the structure of an interconnected lowvoltage supply network, an interconnected reset signal supply network,and an interconnected high voltage supply network in a display panel insome embodiments according to the present disclosure.

FIG. 6B is a diagram illustrating the structure of an interconnected lowvoltage supply network in a display panel in some embodiments accordingto the present disclosure.

FIG. 6C is a diagram illustrating the structure of an interconnectedreset signal supply network in a display panel in some embodimentsaccording to the present disclosure.

FIG. 6D is a diagram illustrating the structure of an interconnectedhigh voltage supply network in a display panel in some embodimentsaccording to the present disclosure.

FIG. 7A is a schematic diagram illustrating the structure in a firstregion ZR1 in FIG. 1 .

FIG. 7B is a diagram illustrating the structure of a first signal linelayer in a first region ZR1 depicted in FIG. 7A.

FIG. 7C is a diagram illustrating the structure of a second signal linelayer in a first region ZR1 depicted in FIG. 7A.

FIG. 7D is a diagram illustrating the structure of a secondplanarization layer in a first region ZR1 depicted in FIG. 7A.

FIG. 7E is a diagram illustrating the structure of an anode layer in afirst region ZR1 depicted in FIG. 7A.

FIG. 7F is a diagram illustrating the structure of a third planarizationlayer in a first region ZR1 depicted in FIG. 7A.

FIG. 7G is a diagram illustrating the structure of a cathode layer in afirst region ZR1 depicted in FIG. 7A.

FIG. 8 is a cross-sectional view along an F-F′ line in FIG. 7A.

FIG. 9A shows an IR drop in a display panel in some embodimentsaccording to the present disclosure.

FIG. 9B shows an IR drop in a related display panel without aninterconnected low voltage supply network.

FIG. 10A is a schematic diagram illustrating the structure in a secondzoom-in region ZR2 in FIG. 1 .

FIG. 10B is a schematic diagram illustrating the structure of lowvoltage signal lines in FIG. 10A.

FIG. 10C is a schematic diagram illustrating the structure of highvoltage signal lines in FIG. 10A.

FIG. 10D is a schematic diagram illustrating the structure of resetsignal lines in FIG. 10A.

FIG. 11A is a diagram illustrating the structure of a first sub-networkof an interconnected low voltage supply network in some embodimentsaccording to the present disclosure.

FIG. 11B is a diagram illustrating the structure of a second sub-networkof an interconnected low voltage supply network in some embodimentsaccording to the present disclosure.

FIG. 11C is a diagram illustrating the structure of an interconnectedlow voltage supply network comprising a first sub-network and a secondsub-network in some embodiments according to the present disclosure.

FIG. 12A is a diagram illustrating the structure of a plurality of firstlow voltage signal lines of an interconnected low voltage supply networkin some embodiments according to the present disclosure.

FIG. 12B is a diagram illustrating the structure of a sub-network of aplurality of second low voltage signal lines of an interconnected lowvoltage supply network in some embodiments according to the presentdisclosure.

FIG. 12C is a diagram illustrating the structure of an interconnectedlow voltage supply network comprising a plurality of first low voltagesignal lines and a sub-network of a plurality of second low voltagesignal lines in some embodiments according to the present disclosure.

DETAILED DESCRIPTION

The disclosure will now be described more specifically with reference tothe following embodiments. It is to be noted that the followingdescriptions of some embodiments are presented herein for purpose ofillustration and description only. It is not intended to be exhaustiveor to be limited to the precise form disclosed.

The present disclosure provides, inter alia, a display panel thatsubstantially obviate one or more of the problems due to limitations anddisadvantages of the related art. In one aspect, the present disclosureprovides a display panel including a plurality of subpixels. Arespective subpixel includes a respective light emitting element and arespective pixel driving circuit. In some embodiments, the display panelincludes a plurality of light emitting elements and an interconnectedfirst voltage supply network configured to provide a first voltagesignal to cathodes of the plurality of light emitting elements.Optionally, the interconnected first voltage supply network includessignal lines in a display area of the display panel. The display area isat least partially surrounded by a peripheral area. The signal linesinclude a plurality of first signal lines in a first signal line layerand a plurality of second signal lines in a second signal line layer.The display panel further includes a planarization layer between thefirst signal line layer and the second signal line layer. The pluralityof first signal lines are electrically connected to the plurality ofsecond signal lines. In one example, a first voltage signal line is alow voltage signal line, and a second voltage signal line is a highvoltage signal line.

As used herein, the term “display area” refers to an area of the displaypanel where an image is actually displayed. Optionally, the display areamay include both a subpixel region and an inter-subpixel region. Asubpixel region refers to a light emission region of a subpixel, such asa region corresponding to a pixel electrode in a liquid crystal displayor a region corresponding to a light emissive layer in an organic lightemitting display. An inter-subpixel region refers to a region betweenadjacent subpixel regions, such as a region corresponding to a blackmatrix in a liquid crystal display or a region corresponding a pixeldefinition layer in an organic light emitting display. Optionally, theinter-subpixel region is a region between adjacent subpixel regions in asame pixel. Optionally, the inter-subpixel region is a region betweentwo adjacent subpixel regions from two adjacent pixels.

As used herein the term “peripheral area” refers to an area of a displaypanel where various circuits and wires are provided to transmit signalsto the display substrate. To increase the transparency of the displaypanel, non-transparent or opaque components of the display panel (e.g.,battery, printed circuit board, metal frame), can be disposed in theperipheral area rather than in the display areas.

Various appropriate light emitting elements may be used in the presentdisplay panel. Examples of appropriate light emitting elements includeorganic light emitting diodes, quantum dots light emitting diodes, andmicro light emitting diodes. Optionally, the light emitting element ismicro light emitting diode. Optionally, the light emitting element is anorganic light emitting diode including an organic light emitting layer.

FIG. 1 is a schematic diagram illustrating the structure of a displaypanel in some embodiments according to the present disclosure. Referringto FIG. 1 , the display panel in some embodiments includes aninterconnected low voltage supply network VSSN. The interconnected lowvoltage supply network VSSN is configured to provide a low voltagesignal to cathodes of the plurality of light emitting elements. Theinterconnected low voltage supply network VSSN includes signal lines ina display area DA of the display panel. The display panel furtherincludes one or more integrated circuits (e.g., IC1, IC2, IC3, and IC4)in a peripheral area PA. The display panel further includes one or morehigh voltage signal line VDD, one or more reset signal line VIN, and agate-on-array circuit GOA.

In some embodiments, the interconnected low voltage supply network VSSNincludes a plurality of first low voltage signal lines Vss1 respectivelyalong a first direction DR1; and a plurality of second low voltagesignal lines Vss2 respectively along a second direction DR2. The firstdirection DR1 and the second direction DR2 are different from eachother. The plurality of first low voltage signal lines Vss1 respectivelycross over the plurality of second low voltage signal lines Vss2.

FIG. 2 is a plan view of a display panel in some embodiments accordingto the present disclosure. Referring to FIG. 2 , the display panelincludes an array of subpixels Sp. Each subpixel includes an electroniccomponent, e.g., a light emitting element. In one example, the lightemitting element is driven by a respective pixel driving circuit PDC.The display panel includes a plurality of gate lines GL, a plurality ofdata lines DL, and a plurality of high voltage signal lines Vdd. Lightemission in a respective subpixel is driven by a respective pixeldriving circuit PDC. In one example, a high voltage signal is input,through a respective one of the plurality of high voltage signal linesVdd, to the respective pixel driving circuit PDC connected to an anodeof the light emitting element; a low voltage signal is input to acathode of the light emitting element. A voltage difference between thehigh voltage signal (e.g., the VDD signal) and the low voltage signal(e.g., the VSS signal) is a driving voltage ΔV that drives lightemission in the light emitting element.

The display panel in some embodiments includes a plurality of subpixels.In some embodiments, the plurality of subpixels includes a respectivefirst subpixel, a respective second subpixel, a respective thirdsubpixel, and a respective fourth subpixel. Optionally, a respectivepixel of the display panel includes the respective first subpixel, therespective second subpixel, the respective third subpixel, and therespective fourth subpixel. The plurality of subpixels in the displaypanel are arranged in an array. In one example, the array of theplurality of subpixels includes a S1-S2-S3-S4 format repeating array, inwhich S1 stands for the respective first subpixel, S2 stands for therespective second subpixel, S3 stands for the respective third subpixel,and S4 stands for the respective fourth subpixel. In another example,the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, in which C1 stands forthe respective first subpixel of a first color, C2 stands for therespective second subpixel of a second color, C3 stands for therespective third subpixel of a third color, and C4 stands for therespective fourth subpixel of a fourth color. In another example, theS1-S2-S3-S4 format is a C1-C2-C3-C2′ format, in which C1 stands for therespective first subpixel of a first color, C2 stands for the respectivesecond subpixel of a second color, C3 stands for the respective thirdsubpixel of a third color, and C2′ stands for the respective fourthsubpixel of the second color. In another example, the C1-C2-C3-C2′format is a R-G-B-G format, in which the respective first subpixel is ared subpixel, the respective second subpixel is a green subpixel, therespective third subpixel is a blue subpixel, and the respective fourthsubpixel is a green subpixel.

In some embodiments, a minimum repeating unit of the plurality ofsubpixels of the display panel includes the respective first subpixel,the respective second subpixel, the respective third subpixel, and therespective fourth subpixel. Optionally, each of the respective firstsubpixel, the respective second subpixel, the respective third subpixel,and the respective fourth subpixel, includes the first transistor T1,the second transistor T2, the third transistor T3, the fourth transistorT4, the fifth transistor T5, the sixth transistor T6, and the drivingtransistor Td.

Various appropriate pixel driving circuits may be used in the presentdisplay panel. Examples of appropriate driving circuits include 3T1C,2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In someembodiments, the respective one of the plurality of pixel drivingcircuits is an 7T1C driving circuit. Various appropriate light emittingelements may be used in the present display panel. Examples ofappropriate light emitting elements include organic light emittingdiodes, quantum dots light emitting diodes, and micro light emittingdiodes. Optionally, the light emitting element is micro light emittingdiode. Optionally, the light emitting element is an organic lightemitting diode including an organic light emitting layer.

FIG. 3 is a circuit diagram illustrating the structure of a pixeldriving circuit in some embodiments according to the present disclosure.Referring to FIG. 3 , in some embodiments, the respective pixel drivingcircuit includes a driving transistor Td; a storage capacitor Cst havinga first capacitor electrode Ce1 and a second capacitor electrode Ce2; afirst transistor T1 having a gate electrode connected to a respectivefirst reset control signal line of a plurality of first reset controlsignal line rst1, a source electrode connected to a respective resetsignal line VintN in a present stage of a plurality of reset signalline, and a drain electrode connected to a first capacitor electrode Ce1of the storage capacitor Cst and a gate electrode of the drivingtransistor Td; a second transistor T2 having a gate electrode connectedto a respective gate line of a plurality of gate lines GL, a sourceelectrode connected to a respective data line of a plurality of datalines DL, and a drain electrode connected to a source electrode of thedriving transistor Td; a third transistor T3 having a gate electrodeconnected to the respective gate line, a source electrode connected tothe first capacitor electrode Ce1 of the storage capacitor Cst and thegate electrode of the driving transistor Td, and a drain electrodeconnected to a drain electrode of the driving transistor Td; a fourthtransistor T4 having a gate electrode connected to a respective lightemitting control signal line of a plurality of light emitting controlsignal lines em, a source electrode connected to a respective voltagesupply line of a plurality of high voltage signal lines Vdd, and a drainelectrode connected to the source electrode of the driving transistor Tdand the drain electrode of the second transistor T2; a fifth transistorT5 having a gate electrode connected to the respective light emittingcontrol signal line, a source electrode connected to drain electrodes ofthe driving transistor Td and the third transistor T3, and a drainelectrode connected to an anode of a light emitting element LE; and asixth transistor T6 having a gate electrode connected to a respectivesecond reset control signal line of a plurality of second reset controlsignal lines rst2, a source electrode connected to a reset signal lineVint(N+1) in the next adjacent stage of the plurality of reset signalline, and a drain electrode connected to the drain electrode of thefifth transistor and the anode of the light emitting element LE. Thesecond capacitor electrode Ce2 is connected to the respective voltagesupply line and the source electrode of the fourth transistor T4.

Referring to FIG. 3 , in some embodiments, the third transistor T3 is a“double gate” transistor, and the first transistor T1 is a “double gate”transistor. Optionally, in a “double gate” first transistor, the activelayer of the first transistor crosses over a respective reset controlsignal lines twice (alternatively, the respective reset control signalline crosses over the active layer of the first transistor T1 twice).Similarly, in a “double gate” third transistor, the active layer of thethird transistor T3 crosses over a respective gate line of the pluralityof gate lines GL twice (alternatively, the respective gate line crossesover the active layer of the third transistor T3 twice).

The pixel driving circuit further include a first node N1, a second nodeN2, a third node N3, and a fourth node N4. The first node N1 isconnected to the gate electrode of the driving transistor Td, the firstcapacitor electrode Ce1, and the source electrode of the thirdtransistor T3. The second node N2 is connected to the drain electrode ofthe fourth transistor T4, the drain electrode of the second transistorT2, and the source electrode of the driving transistor Td. The thirdnode N3 is connected to the drain electrode of the driving transistorTd, the drain electrode of the third transistor T3, and the sourceelectrode of the fifth transistor T5. The fourth node N4 is connected tothe drain electrode of the fifth transistor T5, the drain electrode ofthe sixth transistor T6, the drain electrode of the sensing transistorTs, and the anode of the light emitting element LE.

FIG. 4A is a diagram illustrating the structure of three pixel drivingcircuits for driving light emission of three light emitting elements ofa display panel in some embodiments according to the present disclosure.Referring to FIG. 4A, the display panel in some embodiments includes aplurality of gate lines GL respectively extending along a firstdirection DR1, a plurality of data lines DL respectively extending alonga second direction DR2; a plurality of first high voltage signal linesVdd1 respectively extending along the first direction DR1; a pluralityof second high voltage signal lines Vdd2 respectively extending alongthe second direction DR2; a plurality of first low voltage signal linesVss1 respectively extending along the first direction DR1; a pluralityof second low voltage signal lines Vss2 respectively extending along thesecond direction DR2; a plurality of first reset signal lines Vint1respectively extending along the first direction DR1; and a plurality ofsecond reset signal lines Vint2 respectively extending along the seconddirection DR2. The plurality of first low voltage signal lines Vss1respectively cross over the plurality of second low voltage signal linesVss2. The plurality of first reset signal lines Vint1 respectively crossover the plurality of second reset signal lines Vint2. The plurality offirst high voltage signal lines Vdd1 respectively cross over theplurality of second high voltage signal lines Vdd2. Optionally, thedisplay panel further includes a plurality of first reset control signallines rst1 respectively extending along the first direction DR1; aplurality of second reset control signal lines rst2 respectivelyextending along the first direction DR1; and a plurality of lightemitting control signal lines em respectively extending along the firstdirection DR1. Corresponding positions of the plurality of transistorsin a respective pixel driving circuit are PDC depicted in FIG. 4A. Therespective pixel driving circuit PDC includes the first transistor T1,the second transistor T2, the third transistor T3, the fourth transistorT4, the fifth transistor T5, the sixth transistor T6, the sensingtransistor Ts, and the driving transistor Td.

FIG. 4B is a diagram illustrating the structure of a semiconductormaterial layer in a display panel depicted in FIG. 4A. FIG. 4C is adiagram illustrating the structure of a first conductive layer in adisplay panel depicted in FIG. 4A. FIG. 4D is a diagram illustrating thestructure of a second conductive layer in a display panel depicted inFIG. 4A. FIG. 4E is a diagram illustrating the structure of a firstsignal line layer in a display panel depicted in FIG. 4A. FIG. 3F is adiagram illustrating the structure of a second signal line layer in adisplay panel depicted in FIG. 4A. FIG. 5A is a cross-sectional viewalong an A-A′ line in FIG. 4A. Referring to FIG. 4A to FIG. 4F, and FIG.5A, in some embodiments, the display panel includes a base substrate BS,a semiconductor material layer SML on the base substrate BS, a gateinsulating layer GI on a side of the semiconductor material layer SMLaway from the base substrate BS, a first conductive layer CT1 on a sideof the gate insulating layer GI away from the semiconductor materiallayer SML, an insulating layer IN on a side of the first conductivelayer away from the gate insulating layer GI, a second conductive layerCT2 on a side of the insulating layer IN away from the first conductivelayer CT1, an inter-layer dielectric layer ILD on a side of the secondconductive layer CT2 away from the insulating layer IN, a first signalline layer SL1 on a side of the inter-layer dielectric layer ILD awayfrom the second conductive layer CT2, a planarization layer PLN on aside of the first signal line layer SL1 away from the inter-layerdielectric layer ILD, and a second signal line layer SL2 on a side ofthe planarization layer PLN1 away from the first signal line layer SL1.

Referring to FIG. 3 , FIG. 4A, and FIG. 4B, in some embodiments, thesemiconductor material layer has a unitary structure. In FIG. 4B, therespective pixel driving circuit is annotated with labels indicatingregions corresponding to the plurality of transistors in the respectivepixel driving circuit, including the first transistor T1, the secondtransistor T2, the third transistor T3, the fourth transistor T4, thefifth transistor T5, the sixth transistor T6, and the driving transistorTd. The respective pixel driving circuit is further annotated withlabels indicating components of each of the plurality of transistors inthe pixel driving circuit. For example, the first transistor T1 includesan active layer ACT1, a source electrode S1, and a drain electrode D1.The second transistor T2 includes an active layer ACT2, a sourceelectrode S2, and a drain electrode D2. The third transistor T3 includesan active layer ACT3, a source electrode S3, and a drain electrode D3.The fourth transistor T4 includes an active layer ACT4, a sourceelectrode S4, and a drain electrode D4. The fifth transistor T5 includesan active layer ACT5, a source electrode S5, and a drain electrode D5.The sixth transistor T6 includes an active layer ACT6, a sourceelectrode S6, and a drain electrode D6. The driving transistor Tdincludes an active layer ACTd, a source electrode Sd, and a drainelectrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4,ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, andTd) in the respective pixel driving circuit are parts of a unitarystructure. In another example, the active layers (ACT1, ACT2, ACT3,ACT4, ACT5, ACT6, and ACTd), the source electrodes (S1, S2, S3, S4, S5,S6, and Sd), and the drain electrodes (D1, D2, D3, D4, D5, D6, and Dd)of the transistors (T1, T2, T3, T4, T5, T6, and Td) in the respectivepixel driving circuit are parts of a unitary structure. In anotherexample, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, andACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are in a samelayer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4,ACT5, ACT6, and ACTd), the source electrodes (S1, S2, S3, S4, S5, S6,Ss, and Sd), and the drain electrodes (D1, D2, D3, D4, D5, D6, and Dd)of the transistors (T1, T2, T3, T4, T5, T6, and Td) are in a same layer.

Referring to FIG. 4B, in some embodiments, the unitary structure of thesemiconductor material layer further includes the plurality of firstreset signal lines Vint1. The plurality of first reset signal linesVint1 are in a same layer as at least the active layers (e.g., ACT1,ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of one or more the transistors(e.g., T1, T2, T3, T4, T5, T6, and Td).

As used herein, the active layer refers to a component of the transistorcomprising at least a portion of the semiconductor material layer whoseorthographic projection on the base substrate overlaps with anorthographic projection of a gate electrode on the base substrate. Asused herein, a source electrode refers to a component of the transistorconnected to one side of the active layer, and a drain electrode refersto a component of the transistor connected to another side of the activelayer. In the context of a double-gate type transistor (for example, thethird transistor T3), the active layer refers to a component of thetransistor comprising a first portion of the semiconductor materiallayer whose orthographic projection on the base substrate overlaps withan orthographic projection of a first gate on the base substrate, asecond portion of the semiconductor material layer whose orthographicprojection on the base substrate overlaps with an orthographicprojection of a second gate on the base substrate, and a third portionbetween the first portion and the second portion. In the context of adouble-gate type transistor, a source electrode refers to a component ofthe transistor connected to a side of the first portion distal to thethird portion, and a drain electrode refers to a component of thetransistor connected to a side of the second portion distal to the thirdportion.

Referring to FIG. 3 , FIG. 4A, and FIG. 4C, the first conductive layerin some embodiments includes a gate electrode G1 of the first transistorT1, a gate electrode G3 of the third transistor T3, a gate electrode G6of the sixth transistor T6, a plurality of light emitting control signallines em, and a first capacitor electrode Ce1 of the storage capacitorCst. Various appropriate electrode materials and various appropriatefabricating methods may be used to make the first conductive layer. Forexample, a conductive material may be deposited on the substrate by aplasma-enhanced chemical vapor deposition (PECVD) process and patterned.Examples of appropriate conductive materials for making the firstconductive layer include, but are not limited to, aluminum, copper,molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy,molybdenum aluminum alloy, aluminum chromium alloy, copper chromiumalloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, andthe like. Optionally, the gate electrode G1 of the first transistor T1,the gate electrode G3 of the third transistor T3, the gate electrode G6of the sixth transistor T6, the plurality of light emitting controlsignal lines em, and the first capacitor electrode Ce1 are in a samelayer.

As used herein, the term “same layer” refers to the relationship betweenthe layers simultaneously formed in the same step. In one example, theplurality of light emitting control signal lines em and the firstcapacitor electrode Ce1 are in a same layer when they are formed as aresult of one or more steps of a same patterning process performed in asame layer of material. In another example, the plurality of lightemitting control signal lines em and the first capacitor electrode Ce1can be formed in a same layer by simultaneously performing the step offorming the plurality of light emitting control signal lines em, and thestep of forming the first capacitor electrode Ce1. The term “same layer”does not always mean that the thickness of the layer or the height ofthe layer in a cross-sectional view is the same.

In some embodiments, a respective gate line of the plurality of gatelines comprises a plurality of metal blocks (e.g., G3 in FIG. 4C) spacedapart from each other in a first conductive layer, and a metal line(e.g., GL in FIG. 4E) along a first direction in the first signal linelayer. The signal line along the first direction is connected to theplurality of metal blocks, respectively. The metal line in the firstsignal line layer can be made with a metallic material having arelatively low resistance, as compared to the metallic material in thefirst conductive layer. By having this design, the overall resistance ofthe gate line can be lowered.

In some embodiments, referring to FIG. 4A to FIG. 4C, and FIG. 5A, arespective metal block of the plurality of metal blocks G3 has a Lshape. An orthographic projection of a first channel part of the activelayer ACT3 of the third transistor T3 on the base substrate BS overlapswith an orthographic projection of a first metal portion of therespective metal block of the plurality of metal blocks G3 on the basesubstrate BS. An orthographic projection of a second channel part of theactive layer ACT3 of the third transistor T3 on the base substrate BSoverlaps with an orthographic projection of a second metal portion ofthe respective metal block of the plurality of metal blocks G3 on thebase substrate BS. The first metal portion and the second metal portionare a first gate electrode and a second gate electrode of the thirdtransistor T3.

Referring to FIG. 3 , FIG. 4A, and FIG. 4D, the second conductive layerin some embodiments includes a second capacitor electrode Ce2 of thestorage capacitor Cst. Various appropriate conductive materials andvarious appropriate fabricating methods may be used to make the secondconductive layer. For example, a conductive material may be deposited onthe substrate by a plasma-enhanced chemical vapor deposition (PECVD)process and patterned. Examples of appropriate conductive materials formaking the second conductive layer include, but are not limited to,aluminum, copper, molybdenum, chromium, aluminum copper alloy, coppermolybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy,copper chromium alloy, molybdenum chromium alloy, copper molybdenumaluminum alloy, and the like.

Referring to FIG. 3 , FIG. 4A, and FIG. 4E, the first signal line layerin some embodiments includes a plurality of first low voltage signallines Vss1, a plurality of first reset control signal lines rst1, aplurality of gate lines GL, a plurality of first high voltage signallines Vdd1, a plurality of second reset control signal lines rst2, and anode connecting line Cln. Referring to FIG. 5A, the node connecting lineCln connects the first capacitor electrode Ce1 and the source electrodeS3 of the third transistor T3 in a respective pixel driving circuittogether. Various appropriate conductive materials and variousappropriate fabricating methods may be used to make the first signalline layer. For example, a conductive material may be deposited on thesubstrate by a plasma-enhanced chemical vapor deposition (PECVD) processand patterned. Examples of appropriate conductive materials for makingthe first signal line layer include, but are not limited to, aluminum,copper, molybdenum, chromium, aluminum copper alloy, copper molybdenumalloy, molybdenum aluminum alloy, aluminum chromium alloy, copperchromium alloy, molybdenum chromium alloy, copper molybdenum aluminumalloy, and the like. Optionally, the plurality of first low voltagesignal lines Vss1, the plurality of first reset control signal linesrst1, the plurality of gate lines GL, the plurality of first highvoltage signal lines Vdd1, the plurality of second reset control signallines rst2, and the node connecting line Cln are in a same layer.

In some embodiments, the respective first reset control signal line rst1include a plurality of first metal blocks spaced apart from each otherin a first conductive layer, and a first metal line along a firstdirection in the first signal line layer, the first metal line along thefirst direction being connected to the plurality of first metal blocks,respectively. In some embodiments, the respective second reset controlsignal line comprises a plurality of second metal blocks spaced apartfrom each other in the first conductive layer, and a second metal linealong the first direction in the first signal line layer, the secondmetal line along the first direction being connected to the plurality ofsecond metal blocks, respectively.

In some embodiments, a respective first low voltage signal line of aplurality of first low voltage signal lines Vss1 includes a first linearportion, a second linear portion, and a connecting portion connectingthe first linear portion and the second linear portion. A virtualextension of the first linear portion crosses over the plurality offirst metal blocks (e.g., G1 in FIG. 4C) of the respective first resetcontrol signal line rst1. A virtual extension of the second linearportion is spaced apart from the plurality of first metal blocks, e.g.,does not cross over the plurality of first metal blocks (e.g., G1 inFIG. 4C) of the respective first reset control signal line rst1. Anorthographic projection of the second linear portion on a base substrateis spaced apart from orthographic projections of the plurality of firstmetal blocks. FIG. 4J is a diagram illustrating a relative positionbetween a respective one of a plurality of first low voltage signallines and a plurality of first metal blocks of a respective first resetcontrol signal line in some embodiments according to the presentdisclosure. Referring to FIG. 4J, a respective first low voltage signalline of a plurality of first low voltage signal lines Vss1 includes afirst linear portion LP1, a second linear portion LP2, and a connectingportion CP connecting the first linear portion LP1 and the second linearportion LP2. A virtual extension VE of the first linear portion LP1crosses over the plurality of first metal blocks (G1) of the respectivefirst reset control signal line rst1. A virtual extension of the secondlinear portion LP2 is spaced apart from the plurality of first metalblocks, e.g., does not cross over the plurality of first metal blocks(G1) of the respective first reset control signal line rst1.

Referring to FIG. 3 , FIG. 4A, and FIG. 4F, the second signal line layerin some embodiments includes a plurality of data line DL, a plurality ofsecond low voltage signal lines Vss2, a plurality of second reset signallines Vint2, and a plurality of second high voltage signal lines Vdd2.Various appropriate conductive materials and various appropriatefabricating methods may be used to make the second signal line layer.For example, a conductive material may be deposited on the substrate bya plasma-enhanced chemical vapor deposition (PECVD) process andpatterned. Examples of appropriate conductive materials for making thesecond signal line layer include, but are not limited to, aluminum,copper, molybdenum, chromium, aluminum copper alloy, copper molybdenumalloy, molybdenum aluminum alloy, aluminum chromium alloy, copperchromium alloy, molybdenum chromium alloy, copper molybdenum aluminumalloy, and the like. Optionally, the plurality of data line DL, theplurality of second low voltage signal lines Vss2, the plurality ofsecond reset signal lines Vint2, and the plurality of second highvoltage signal lines Vdd2 are in a same layer.

Referring to FIG. 4F, in some embodiments, a minimal distance between arespective second reset signal line of the plurality of second resetsignal lines Vint2 and a respective second low voltage signal line ofthe plurality of second low voltage signal lines Vss2 that is mostadjacent to the respective second reset signal line is less than aminimal distance between the respective second reset signal line and arespective data line of a plurality of data line DL that is mostadjacent to the respective second reset signal line. In someembodiments, a total of three data lines and a total of one second lowvoltage signal line are between two most adjacent second reset signallines of the plurality of second reset signal lines Vint2. Optionally, atotal of three data lines, a total of one second low voltage signalline, and a total of three second high voltage signal lines are betweentwo most adjacent second reset signal lines of the plurality of secondreset signal lines Vint2.

Referring to FIG. 3 , FIG. 4D, FIG. 4E, and FIG. 5A, in someembodiments, an orthographic projection of the second capacitorelectrode Ce2 on a base substrate BS completely covers, with a margin,an orthographic projection of the first capacitor electrode Ce1 on thebase substrate BS except for a hole region H in which a portion of thesecond capacitor electrode Ce2 is absent. In some embodiments, the firstsignal line layer includes a node connecting line Cln on a side of theinter-layer dielectric layer ILD away from the second capacitorelectrode Ce2. The node connecting line Cln is in a same layer as theplurality of first low voltage signal lines Vss1, the plurality of firstreset control signal lines rst1, the plurality of gate lines GL, theplurality of first high voltage signal lines Vdd1, and the plurality ofsecond reset control signal lines rst2. Optionally, the display panelfurther includes a first connecting via cv1 in the hole region H andextending through the inter-layer dielectric layer ILD and theinsulating layer IN. Optionally, the node connecting line Cln isconnected to the first capacitor electrode Ce1 through the firstconnecting via cv1. In some embodiments, the first capacitor electrodeCe1 is on a side of the gate insulating layer IN away from the basesubstrate BS. Optionally, the display panel further includes a firstconnecting via cv1 and a second connecting via cv2. The first connectingvia cv1 is in the hole region H and extends through the inter-layerdielectric layer ILD and the insulating layer IN. The second connectingvia cv2 extends through the inter-layer dielectric layer ILD, theinsulating layer IN, and the gate insulating layer GI. Optionally, thenode connecting line Cln is connected to the first capacitor electrodeCe1 through the first connecting via cv1, and is connected nodeconnecting line Cln is connected the semiconductor material layer SMLthrough the second connecting via cv2. Optionally, the node connectingline Cln is connected to the source electrode S3 of third transistor T3,as depicted in FIG. 5A.

In some embodiments, referring to FIG. 4D, the second capacitorelectrode Ce2 includes an extension E extending away from an electrodemain body emb of the second capacitor electrode Ce2. Referring to FIG.4A, an orthographic projection of the extension E on a base substrate atleast partially overlaps with an orthographic projection of an activelayer of a third transistor T3 of the respective pixel driving circuit.A portion of the extension E is between a first node N1 of therespective pixel driving circuit and a respective data line of theplurality of data lines dl, configured to prevent interference fromsignals passing through the respective data line to the first node N1. Aportion of the extension E is between the node connecting line Cln and arespective data line of the plurality of data lines dl.

By having the extension E, the active layer of the third transistor canbe protected from irradiation. Because the extension E is part of thesecond capacitor electrode, the extension E has a stable voltage level,obviating the need to electrically connecting the extension E to asignal line having a stable voltage level.

Referring to FIG. 4A to FIG. 4F, the third transistor T3 includes afirst gate electrode and a second gate electrode. An orthographicprojection of the first gate electrode on the base substrate overlapswith an orthographic projection of a first channel part of the ACT3 ofthe third transistor T3 on the base substrate. An orthographicprojection of the second gate electrode on the base substrate overlapswith an orthographic projection of a second channel part of the activelayer ACT3 of the third transistor T3 on the base substrate. The activelayer ACT3 of the third transistor T3 further includes a portionconnecting the first channel part and the second channel part. Theorthographic projection of the extension E on a base substrate at leastpartially overlaps with an orthographic projection of the portionconnecting the first channel part and the second channel part on thebase substrate.

In some embodiments, the extension E includes a first extension partalong a first direction DR1 and a second extension part along a seconddirection DR2. The first extension part connects the second extensionpart with the electrode main body emb of the second capacitor electrodeCe2. In some embodiments, an orthographic projection of the secondextension part on the base substrate at least partially overlaps withthe orthographic projection of the active layer ACT3 of the thirdtransistor T3 of the respective pixel driving circuit on the basesubstrate.

In some embodiments, the second extension part includes a shieldingportion and a non-shielding portion. An orthographic projection of theshielding portion on the base substrate at least partially overlaps withthe orthographic projection of the active layer ACT3 of the thirdtransistor T3 of the respective pixel driving circuit on the basesubstrate. An orthographic projection of the non-shielding portion onthe base substrate is non-overlapping with the orthographic projectionof the active layer ACT3 of the third transistor T3 of the respectivepixel driving circuit on the base substrate. A line width of theshielding portion is greater than a line width of the non-shieldingportion, ensuring that the active layer ACT3 of the third transistor T3of the respective pixel driving circuit is shielded.

In some embodiments, an orthographic projection of the first extensionpart on the base substrate at least partially overlaps with anorthographic projection of the node connecting line Cln on the basesubstrate. The first extension part is between the node connecting lineCln and a respective data line of the plurality of data lines dl. Thefirst extension part between the node connecting line Cln and therespective data line is configured to prevent interference to the firstnode N1 from signals passing through the respective data line.

In some embodiments, an orthographic projection of the first extensionpart on a line extending along the second direction at least partiallyoverlaps with an orthographic projection of the node connecting line onthe line. The first extension part is configured to prevent interferenceto the first node N1 from signals transmitting along the firstdirection.

In some embodiments, an orthographic projection of the respective one ofthe plurality of second high voltage signal lines Vdd2 on the basesubstrate covers an orthographic projection of the node connecting lineCln on the base substrate. By having the respective one of the pluralityof second high voltage signal lines Vdd2 shielding the node connectingline Cln, a voltage level at the node N1 can be stabilized because aconstant voltage level is provided to the respective one of theplurality of second high voltage signal lines Vdd2.

In some embodiments, an orthographic projection of the respective one ofthe plurality of second high voltage signal lines Vdd2 on the basesubstrate at least partially overlaps with an orthographic projection ofat least one gate electrode of the third transistor T3 on the basesubstrate. By having the respective one of the plurality of second highvoltage signal lines Vdd2 shielding the at least one gate electrode ofthe third transistor T3, a voltage level at the node N1 can be furtherstabilized.

FIG. 6A is a diagram illustrating the structure of an interconnected lowvoltage supply network, an interconnected reset signal supply network,and an interconnected high voltage supply network in a display panel insome embodiments according to the present disclosure. The interconnectedlow voltage supply network includes signal lines in a display area ofthe display panel. The interconnected low voltage supply network isconfigured to provide a low voltage signal to cathodes of the pluralityof light emitting elements. The interconnected reset signal supplynetwork is configured to provide a reset signal to a plurality of pixeldriving circuits. The interconnected reset signal supply networkincludes signal lines in a display area of the display panel. Theinterconnected high voltage supply network is configured to provide ahigh voltage signal to a plurality of pixel driving circuits. Theinterconnected high voltage supply network includes signal lines in adisplay area of the display panel. In one example, a first voltagesignal line is a low voltage signal line, and a second voltage signalline is a high voltage signal line.

FIG. 6B is a diagram illustrating the structure of an interconnected lowvoltage supply network in a display panel in some embodiments accordingto the present disclosure. Referring to FIG. 6A and FIG. 6B, theinterconnected low voltage supply network in some embodiments includes aplurality of first low voltage signal lines Vss1 respectively along afirst direction DR1; and a plurality of second low voltage signal linesVss2 respectively along a second direction DR2. The plurality of firstlow voltage signal lines Vss1 respectively cross over the plurality ofsecond low voltage signal lines Vss2. A respective one of the pluralityof first low voltage signal lines Vss1 is connected to at least multipleones of the plurality of second low voltage signal lines Vss2. Arespective one of the plurality of second low voltage signal lines Vss2is connected to at least multiple ones of the plurality of first lowvoltage signal lines Vss1.

FIG. 5B is a cross-sectional view along a B-B′ line in FIG. 4A.Referring to FIG. 5B, FIG. 6A, and FIG. 6B, in some embodiments, thefirst signal line layer SL1 includes the plurality of first low voltagesignal lines Vss1, and the second signal line layer SL2 includes theplurality of second low voltage signal lines Vss2. The plurality offirst low voltage signal lines Vss1 and the plurality of second lowvoltage signal lines Vss2 interconnect through first vias v1 srespectively extending through the planarization layer PLN. At leastsome of the first vias are in the display area. A respective one of theplurality of first low voltage signal lines Vss1 is connected to atleast multiple ones of the plurality of second low voltage signal linesVss2 respectively through multiple first vias extending through theplanarization layer PLN. A respective one of the plurality of second lowvoltage signal lines Vss2 is connected to at least multiple ones of theplurality of first low voltage signal lines Vss1 respectively throughmultiple first vias extending through the planarization layer PLN.

FIG. 6C is a diagram illustrating the structure of an interconnectedreset signal supply network in a display panel in some embodimentsaccording to the present disclosure. Referring to FIG. 6A and FIG. 6C,the interconnected reset signal supply network in some embodimentsincludes a plurality of first reset signal lines Vint1 respectivelyalong a first direction DR1; and a plurality of second reset signallines Vint2 respectively along a second direction DR2. The plurality offirst reset signal lines Vint1 respectively cross over the plurality ofsecond reset signal lines Vint2. A respective one of the plurality offirst reset signal lines Vint1 is connected to at least multiple ones ofthe plurality of second reset signal lines Vint2. A respective one ofthe plurality of second reset signal lines Vint2 is connected to atleast multiple ones of the plurality of first reset signal lines Vint1.

FIG. 5C is a cross-sectional view along a C-C′ line in FIG. 4A.Referring to FIG. 5C, FIG. 6A, and FIG. 6C, in some embodiments, thesemiconductor material layer SML includes the plurality of first resetsignal lines Vint1, and the second signal line layer SL2 includes theplurality of second reset signal lines Vint2. The plurality of firstreset signal lines Vint1 and the plurality of second reset signal linesVint2 interconnect through second vias v2 s respectively extendingthrough at least the planarization layer PLN. In one example, theplurality of first reset signal lines Vint1 and the plurality of secondreset signal lines Vint2 interconnect through second vias v2 s, arespective second via extending through the planarization layer PLN, theinter-layer dielectric layer ILD, the insulating layer IN, and the gateinsulating layer GI. A respective one of the plurality of first resetsignal lines Vint1 is connected to at least multiple ones of theplurality of second reset signal lines Vint2 respectively throughmultiple second vias extending through at least the planarization layerPLN. A respective one of the plurality of second reset signal linesVint2 is connected to at least multiple ones of the plurality of firstreset signal lines Vint1 respectively through multiple second viasextending through at least the planarization layer PLN.

Optionally, the plurality of first reset signal lines Vint1 include asemiconductor material; and the plurality of second reset signal linesVint2 include a metallic material. Optionally, the plurality of firstreset signal lines Vint1 and at least active layers (e.g., ACTd, andACT1 to ACT6) of a plurality of thin film transistors (e.g., Td, and T1to T6) are in the semiconductor material layer SML, and include a samesemiconductor material.

Alternatively, the reset signal lines (one or both of the plurality offirst reset signal lines Vint1 and the plurality of second reset signallines Vint2) may be disposed in the first conductive layer.Alternatively, the reset signal lines (one or both of the plurality offirst reset signal lines Vint1 and the plurality of second reset signallines Vint2) may be disposed in the first signal line layer.Alternatively, the reset signal lines (one or both of the plurality offirst reset signal lines Vint1 and the plurality of second reset signallines Vint2) may be disposed in the second conductive layer.Alternatively, the reset signal lines (one or both of the plurality offirst reset signal lines Vint1 and the plurality of second reset signallines Vint2) may be disposed in the second signal line layer.Alternatively, the plurality of first reset signal lines Vint1 and theplurality of second reset signal lines Vint2 are in a same layer,interconnecting with each other to form a network.

FIG. 6D is a diagram illustrating the structure of an interconnectedhigh voltage supply network in a display panel in some embodimentsaccording to the present disclosure. Referring to FIG. 6A and FIG. 6D,the interconnected high voltage supply network in some embodimentsincludes a plurality of first high voltage signal lines Vdd1respectively along a first direction DR1; and a plurality of second highvoltage signal lines Vdd2 respectively along a second direction DR2. Theplurality of first high voltage signal lines Vdd1 respectively crossover the plurality of second high voltage signal lines Vdd2. Arespective one of the plurality of first high voltage signal lines Vdd1is connected to at least multiple ones of the plurality of second highvoltage signal lines Vdd2. A respective one of the plurality of secondhigh voltage signal lines Vdd2 is connected to at least multiple ones ofthe plurality of first high voltage signal lines Vdd1.

FIG. 5D is a cross-sectional view along a D-D′ line in FIG. 4A.Referring to FIG. 5D, FIG. 6A, and FIG. 6D, in some embodiments, thefirst signal line layer SL1 includes the plurality of first high voltagesignal lines Vdd1, and the second signal line layer SL2 includes theplurality of second high voltage signal lines Vdd2. A respective one ofthe plurality of first high voltage signal lines Vdd1 is connected tosecond capacitor electrode through one or more third vias v3 srespectively extending through the inter-layer dielectric layer ILD. Arespective one of the plurality of first high voltage signal lines Vdd1is connected to at least multiple ones of the plurality of second highvoltage signal lines Vdd2 respectively through multiple third viasextending through the planarization layer PLN. A respective one of theplurality of second high voltage signal lines Vdd2 is connected to atleast multiple ones of the plurality of first high voltage signal linesVdd1 respectively through multiple third vias extending through theplanarization layer PLN. By having the second capacitor electrodeconnected to the respective one of the plurality of first high voltagesignal lines Vdd1, resistance of the respective one of the plurality offirst high voltage signal lines Vdd1 can be reduced.

FIG. 5E is a cross-sectional view along a E-E′ line in FIG. 4A.Referring to FIG. 5E, FIG. 6A, and FIG. 6D, in some embodiments, thefirst signal line layer SL1 includes the plurality of first high voltagesignal lines Vdd1, and the second signal line layer SL2 includes theplurality of second high voltage signal lines Vdd2. A respective one ofthe plurality of first high voltage signal lines Vdd1 is connected tosecond capacitor electrode through one or more third vias v3 srespectively extending through the inter-layer dielectric layer ILD. Arespective one of the plurality of second high voltage signal line Vdd2is connected to a respective one of the plurality of first high voltagesignal lines Vdd1 through one or more fourth vias v4 s respectivelyextending through the planarization layer PLN. A respective one of theplurality of first high voltage signal lines Vdd1 is connected to thesource electrode S4 of the fourth transistor through a third connectingvia cv4 extending through the inter-layer dielectric layer ILD, theinsulating layer IN, and the gate insulating layer GI.

FIG. 4G is a diagram illustrating the structure of a respective one of aplurality of first high voltage signal lines in some embodimentsaccording to the present disclosure. Referring to FIG. 4G, therespective one of a plurality of first high voltage signal lines Vdd1 insome embodiments includes a main body md extending along the firstdirection DR1, a first protrusion pd1 protruding away from the main bodymd along the second direction DR2, and a second protrusion pd2protruding away from the first protrusion pd1 along the second directionDR2. The second protrusion pd2 connects to the main body md through thefirst protrusion pd1. The first protrusion pd1 is a portion of therespective one of a plurality of first high voltage signal lines Vdd1where the respective one of a plurality of first high voltage signallines Vdd1 connects to the second capacitor electrode. The secondprotrusion pd2 is a portion of the respective one of a plurality offirst high voltage signal lines Vdd1 where the respective one of aplurality of first high voltage signal lines Vdd1 connects to the sourceelectrode of the fourth transistor. The second protrusion pd2 is aportion of the respective one of the plurality of second high voltagesignal line Vdd2 where the respective one of the plurality of secondhigh voltage signal line Vdd2 is connected to a respective one of theplurality of first high voltage signal lines Vdd1 through one or morevias. A drain electrode of the fourth transistor is connected to asource electrode of a driving transistor.

FIG. 4H is a diagram illustrating the layout of anodes of light emittingelements with respect to pixel driving circuits of a display panel insome embodiments according to the present disclosure. FIG. 4I is adiagram illustrating the structure of anodes, a first signal line layer,and a second signal line layer in a display panel in some embodimentsaccording to the present disclosure. Referring to FIG. 4H and FIG. 4I,the display panel in some embodiments further includes a plurality ofanodes respectively of the plurality of light emitting elements, forexample, a first anode AD1, a second anode AD2, and a third anode AD3 asdepicted in FIG. 4H. A respective anode is connected to an anode contactpad through a via extending through a second planarization layer (e.g.,PLN2 in FIG. 5A to FIG. 5E), and the anode contact pad is connected to arelay electrode through a via extending through the planarization layer(e.g., PLN in FIG. 5A to FIG. 5E). The relay electrode is connected tothe N4 node (e.g., the drain electrode of the fifth transistor) througha via extending through the inter-layer dielectric layer.

Referring to FIG. 4H, FIG. 4I, FIG. 4E, and FIG. 4F, in one example, thefirst anode AD1 is connected to a first anode contact pad ACP1 through avia extending through the second planarization layer, the first anodecontact pad ACP1 is connected to a first relay electrode RE1 through avia extending through the planarization layer; the second anode AD2 isconnected to a second anode contact pad ACP2 through a via extendingthrough the second planarization layer, the second anode contact padACP2 is connected to a second relay electrode RE2 through a viaextending through the planarization layer; the third anode AD3 isconnected to a third anode contact pad ACP3 through a via extendingthrough the second planarization layer, the third anode contact pad ACP3is connected to a third relay electrode RE3 through a via extendingthrough the planarization layer.

In some embodiments, referring to FIG. 1 , the display panel furtherincludes a gate-on-array circuit GOA in a peripheral area PA of thedisplay panel. The interconnected low voltage supply network VSSNincludes a first peripheral low voltage line pvss1 in the peripheralarea PA on a first side S1 of the display panel. FIG. 7A is a schematicdiagram illustrating the structure in a first zoom-in region ZR1 in FIG.1 . FIG. 7B is a diagram illustrating the structure of a first signalline layer in a first region ZR1 depicted in FIG. 7A. FIG. 7C is adiagram illustrating the structure of a second signal line layer in afirst region ZR1 depicted in FIG. 7A. FIG. 7D is a diagram illustratingthe structure of a second planarization layer in a first region ZR1depicted in FIG. 7A. FIG. 7E is a diagram illustrating the structure ofan anode layer in a first region ZR1 depicted in FIG. 7A. FIG. 7F is adiagram illustrating the structure of a third planarization layer in afirst region ZR1 depicted in FIG. 7A. FIG. 7G is a diagram illustratingthe structure of a cathode layer in a first region ZR1 depicted in FIG.7A. Referring to FIG. 7A to FIG. 7G, and FIG. 1 , the display panel inthe peripheral area PA on the first side S1 of the display panel includea gate-on-array circuit GOA in the first signal line layer on a basesubstrate, a first peripheral low voltage line pvss1 in the secondsignal line layer on a side of the gate-on-array circuit GOA away fromthe base substrate, a second planarization layer PLN2 on a side of thefirst peripheral low voltage line pvss1 away from the gate-on-arraycircuit GOA, an anode metal layer AML in an anode layer on a side of thesecond planarization layer PLN2 away from the first peripheral lowvoltage line pvss1, a third planarization layer PLN3 on a side of theanode metal layer AML away from the second planarization layer PLN2, anda cathode layer CDL on a side of the third planarization layer PLN3 awayfrom the anode metal layer AML.

FIG. 8 is a cross-sectional view along an F-F′ line in FIG. 7A.Referring to FIG. 1 , FIG. 7 , and FIG. 8 , in some embodiments, anorthographic projection of the first peripheral low voltage line pvss1on a base substrate BS at least partially overlaps with an orthographicprojection of the gate-on-array circuit GOA on the base substrate BS.Optionally, the orthographic projection of the first peripheral lowvoltage line pvss1 on a base substrate BS at least 80% (e.g., at least85%, at least 90%, at least 95%, at least 99%) overlaps with theorthographic projection of the gate-on-array circuit GOA on the basesubstrate BS.

Referring to FIG. 8 , the cathode layer CDL is connected to the anodemetal layer AML through one or more first peripheral vias pv1 in theperipheral area and extending through a third planarization layer PLN3,and the anode metal layer AML is connected to the first peripheral firstvoltage line pvss1 through one or more second peripheral vias pv2 in theperipheral area and extending through a second planarization layer PLN2,thereby providing the first voltage signal to the cathodes of theplurality of light emitting elements. The display panel includes aplurality of first gas releasing vias grv1 extending through the firstperipheral first voltage line pvss1 for releasing gases in underneathinsulating layer (e.g., the planarization layer PLN) during afabrication process of the display panel. The display panel furtherincludes a plurality of second gas releasing vias grv2 extending throughthe anode metal layer AML for releasing gases in underneath insulatinglayer (e.g., the second planarization layer PLN2) during a fabricationprocess of the display panel.

In some embodiments, the cathode layer CDL is a unitary cathode layerextending substantially throughout the display panel and functions ascathodes for the plurality of light emitting elements. Optionally, theone or more vias connecting the cathode layer CDL and the anode metallayer AML are limited in the peripheral area PA, and absent in thedisplay area DA. The cathode layer CDL is connected to theinterconnected low voltage supply network VSSN only through the anodemetal layer AML.

In the present display panel, the low voltage line shares a same spaceas the gate-on-array circuit GOA. The display panel can be made with avery narrow bezel. In one example, the present display panel has a bezelwidth on the first side S1 (or the side opposite to the first side S1)of approximately 1.5 mm, as compared to 2.5 mm in a related displaypanel.

Moreover, in the present display panel, the connection between the lowvoltage line and the cathode layer CDL (through the anode metal layer)may be made exclusively in the peripheral area PA (e.g., in the GOAregion), obviating the need of making vias (or any process at all) inthe display area DA to connect the low voltage line and the cathodelayer CDL. The display panel can be fabricated with much lesscomplexity, significantly lowering occurrence of defects in the displaypanel.

The inventors of the present disclosure discover that, surprisingly andunexpectedly, the implementation of the interconnected low voltagesupply network dramatically reduces a degree of voltage drop of the lowvoltage signal (e.g., the VSS signal) throughout the display panel. FIG.9A shows an IR drop in a display panel in some embodiments according tothe present disclosure. FIG. 9B shows an IR drop in a related displaypanel without an interconnected low voltage supply network. In FIG. 9Aand FIG. 9B, a degree of darkness indicates a degree of IR drop in alocal region. Comparing FIG. 9A and FIG. 9B, the degree of voltage dropin the embodiments according to the present disclosure is dramaticallyreduced as compared to the degree of voltage drop in the related displaypanel without an interconnected low voltage supply network. Overall, theIR drop is reduced from 1.5641 V to 1.2337 V (more than 20% reduction).The advantages of the present display panel are particularly meaningfulfor large size display panels. In the related display panel without aninterconnected low voltage supply network, as shown in FIG. 9B, the VSScurrent concentrates at outmost two ports, leading to issues such ashigh current burns. For example, in the related display panel without aninterconnected low voltage supply network, the VSS current at theoutmost port is about 26.6% of the total VSS current. In the displaypanel in some embodiments according to the present disclosure, the VSScurrent at any port is less than 11% of the total VSS current, obviatingthe issue of large current burns.

To accommodate the implementation of the interconnected network in thepresent display panel, the layers and signal lines in the peripheralarea have adopted a novel and unique structure that is advantageous infurther reducing the bezel width, improving voltage uniformitythroughout the display panel, and minimizing occurrence of defects inthe display panel. FIG. 10A is a schematic diagram illustrating thestructure in a second zoom-in region ZR2 in FIG. 1 . FIG. 10B is aschematic diagram illustrating the structure of low voltage signal linesin FIG. 10A. FIG. 10C is a schematic diagram illustrating the structureof high voltage signal lines in FIG. 10A. Referring to FIG. 1 , FIG.10A, FIG. 10B, and FIG. 10C, in some embodiments, the display panelincludes a peripheral high voltage signal line pvdd, a second peripherallow voltage signal line pvss2, and a third peripheral low voltage signalline pvss3 in the peripheral area PA on a second side S2 of the displaypanel. One or more of the plurality of second high voltage signal linesVdd2 are connected to the peripheral high voltage signal line pvdd. Oneor more of the plurality of second low voltage signal lines Vss2 areconnected to the second peripheral low voltage signal line pvss2. Thesecond peripheral low voltage signal line pvss2 and the third peripherallow voltage signal line pvss3 are connected to each other through aplurality of bridges bg. Optionally, the plurality of first low voltagesignal lines, the peripheral high voltage signal line pvdd, and theplurality of bridges are in a first signal line layer SL1 (referring to,e.g., FIG. 5A for layer arrangement of the display panel). Optionally,the plurality of second high voltage signal lines Vdd2, the secondperipheral low voltage signal line pvss2 are in a second signal linelayer SL2. Optionally, the third peripheral low voltage signal linepvss3 includes a first sub-layer in the first signal line layer SL1 anda second sub-layer in the second signal line layer SL2.

FIG. 10D is a schematic diagram illustrating the structure of resetsignal lines in FIG. 10A. Referring to FIG. 1 , FIG. 10A, and FIG. 10D,in some embodiments, the display panel includes a peripheral resetsignal line pvint in the peripheral area PA on a second side S2 of thedisplay panel. One or more of the plurality of second reset signal linesVint2 are connected to the peripheral reset signal line pvint.Optionally, the peripheral reset signal line pvint is in a layerdifferent from the peripheral high voltage signal line pvdd and theperipheral low voltage signal line pvss2. Optionally, the peripheralreset signal line pvint is in a same layer as the plurality of secondreset signal lines Vint2. Optionally, the peripheral reset signal linepvint is in a layer different from the plurality of second reset signallines Vint2. In some embodiments, the peripheral reset signal line pvintincludes a first part p1 and a second part p2. Optionally, the firstpart p1 includes a single layer conductive material in a same layer asthe second signal line layer. Optionally, the second part has adouble-layer structure including conductive materials respectively inthe first signal line layer and the second signal line layer.

Referring to FIG. 10A, in some embodiments, the display panel furtherinclude a anode metal layer AML. In some embodiments, the anode metallayer AML is connected to the peripheral low voltage signal line pvss2through vias extending through one or more insulating layers.

Various appropriate implementations of the interconnected low voltagesupply network may be practiced according to the present disclosure.FIG. 11A is a diagram illustrating the structure of a first sub-networkof an interconnected low voltage supply network in some embodimentsaccording to the present disclosure. FIG. 11B is a diagram illustratingthe structure of a second sub-network of an interconnected low voltagesupply network in some embodiments according to the present disclosure.FIG. 11 C is a diagram illustrating the structure of an interconnectedlow voltage supply network comprising a first sub-network and a secondsub-network in some embodiments according to the present disclosure.Referring to FIG. 11A to FIG. 11C, the interconnected low voltage supplynetwork in some embodiments includes a first sub-network formed by theplurality of first low voltage signal lines Vss1 and a secondsub-network formed by the plurality of second low voltage signal linesVss2. Optionally, the first sub-network is in the first signal linelayer and the second sub-network is in the second signal line layer. Theplurality of first signal lines Vss1 are electrically connected to theplurality of second signal lines Vss2.

In some embodiments, the plurality of first low voltage signal linesVss1 form a sub-network whereas the plurality of second low voltagesignal lines Vss2 do not form a sub-network. In some embodiments, theplurality of second low voltage signal lines Vss2 form a sub-networkwhereas the plurality of first low voltage signal lines Vss1 do not forma sub-network.

FIG. 12A is a diagram illustrating the structure of a plurality of firstlow voltage signal lines of an interconnected low voltage supply networkin some embodiments according to the present disclosure. FIG. 12B is adiagram illustrating the structure of a sub-network of a plurality ofsecond low voltage signal lines of an interconnected low voltage supplynetwork in some embodiments according to the present disclosure. FIG.12C is a diagram illustrating the structure of an interconnected lowvoltage supply network comprising a plurality of first low voltagesignal lines and a sub-network of a plurality of second low voltagesignal lines in some embodiments according to the present disclosure.Referring to FIG. 12A to FIG. 12C, the plurality of first low voltagesignal lines Vss1 are separated from each other and does not form asub-network, whereas the plurality of second low voltage signal linesVss2 form a sub-network. The plurality of first signal lines Vss1 areelectrically connected to the plurality of second signal lines Vss2.

In another aspect, the present invention provides a display apparatus,including the display panel described herein or fabricated by a methoddescribed herein, and one or more integrated circuits connected to thedisplay panel. Examples of appropriate display apparatuses include, butare not limited to, an electronic paper, a mobile phone, a tabletcomputer, a television, a monitor, a notebook computer, a digital album,a GPS, etc. Optionally, the display apparatus is an organic lightemitting diode display apparatus. Optionally, the display apparatus is aliquid crystal display apparatus.

In another aspect, the present disclosure provides a method offabricating a display panel. In some embodiments, the method includesforming a plurality of light emitting elements; and forming aninterconnected low voltage supply network configured to provide a lowvoltage signal to cathodes of the plurality of light emitting elements.Optionally, forming the interconnected low voltage supply networkincludes forming signal lines in a display area of the display panel.

The foregoing description of the embodiments of the invention has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formor to exemplary embodiments disclosed. Accordingly, the foregoingdescription should be regarded as illustrative rather than restrictive.Obviously, many modifications and variations will be apparent topractitioners skilled in this art. The embodiments are chosen anddescribed in order to explain the principles of the invention and itsbest mode practical application, thereby to enable persons skilled inthe art to understand the invention for various embodiments and withvarious modifications as are suited to the particular use orimplementation contemplated. It is intended that the scope of theinvention be defined by the claims appended hereto and their equivalentsin which all terms are meant in their broadest reasonable sense unlessotherwise indicated. Therefore, the term “the invention”, “the presentinvention” or the like does not necessarily limit the claim scope to aspecific embodiment, and the reference to exemplary embodiments of theinvention does not imply a limitation on the invention, and no suchlimitation is to be inferred. The invention is limited only by thespirit and scope of the appended claims. Moreover, these claims mayrefer to use “first”, “second”, etc. following with noun or element.Such terms should be understood as a nomenclature and should not beconstrued as giving the limitation on the number of the elementsmodified by such nomenclature unless specific number has been given. Anyadvantages and benefits described may not apply to all embodiments ofthe invention. It should be appreciated that variations may be made inthe embodiments described by persons skilled in the art withoutdeparting from the scope of the present invention as defined by thefollowing claims. Moreover, no element and component in the presentdisclosure is intended to be dedicated to the public regardless ofwhether the element or component is explicitly recited in the followingclaims.

What is claimed is:
 1. A display panel, comprising a base substrate, aplurality of subpixels, a respective subpixel comprising a respectivelight emitting element and a respective pixel driving circuit; whereinthe respective pixel driving circuit comprises: a third transistor; anda storage capacitor comprising a first capacitor electrode in a firstconductive layer and a second capacitor electrode in a second conductorlayer; wherein the second conductive layer is on a side of the firstconductive layer away from the base substrate; the second capacitorelectrode comprises an extension extending away from an electrode mainbody of the second capacitor electrode; and an orthographic projectionof the extension on the base substrate at least partially overlaps withan orthographic projection of an active layer of the third transistor ofthe respective pixel driving circuit on the base substrate.
 2. Thedisplay panel of claim 1, wherein the third transistor comprises a firstgate electrode and a second gate electrode; an orthographic projectionof the first gate electrode on the base substrate overlaps with anorthographic projection of a first channel part of the active layer ofthe third transistor on the base substrate; an orthographic projectionof the second gate electrode on the base substrate overlaps with anorthographic projection of a second channel part of the active layer ofthe third transistor on the base substrate; the active layer of thethird transistor further comprises a portion connecting the firstchannel part and the second channel part; and the orthographicprojection of the extension on the base substrate at least partiallyoverlaps with an orthographic projection of the portion connecting thefirst channel part and the second channel part on the base substrate. 3.The display panel of claim 1, further comprising a first signal linelayer on a side of the storage capacitor away from the base substrate;wherein multiple second capacitor electrodes respectively from multiplepixel driving circuits are sequentially connected to each other along afirst direction; the first signal line layer comprises a plurality offirst high voltage signal lines respectively along a first direction;and a respective one of the plurality of first high voltage signal linesis connected to the second capacitor electrode.
 4. The display panel ofclaim 1, wherein the extension comprises a first extension part along asecond direction and a second extension part along a first direction;the first extension part connects the second extension part with theelectrode main body of the second capacitor electrode; and anorthographic projection of the second extension part on the basesubstrate at least partially overlaps with the orthographic projectionof the active layer of the third transistor of the respective pixeldriving circuit on the base substrate.
 5. The display panel of claim 4,wherein the second extension part comprises a shielding portion and anon-shielding portion; an orthographic projection of the shieldingportion on the base substrate at least partially overlaps with theorthographic projection of the active layer of the third transistor ofthe respective pixel driving circuit on the base substrate; anorthographic projection of the non-shielding portion on the basesubstrate is non-overlapping with the orthographic projection of theactive layer of the third transistor of the respective pixel drivingcircuit on the base substrate; and a line width of the shielding portionis greater than a line width of the non-shielding portion.
 6. Thedisplay panel of claim 4, wherein the respective pixel driving circuitfurther comprises a driving transistor, and a node connecting lineconnecting a drain electrode of the third transistor with a gateelectrode of the driving transistor; wherein the drain electrode of thethird transistor is connected to the gate electrode of the drivingtransistor; a source electrode of the third transistor is connected to adrain electrode of the driving transistor; and an orthographicprojection of the first extension part on a line extending along thesecond direction at least partially overlaps with an orthographicprojection of the node connecting line on the line.
 7. The display panelof claim 6, further comprising a plurality of data lines; wherein thefirst extension part is between the node connecting line and arespective data line of the plurality of data lines.
 8. The displaypanel of claim 1, further comprising a plurality of gate lines; whereina respective gate line of the plurality of gate lines comprises aplurality of metal blocks spaced apart from each other in a firstconductive layer, and a metal line along a first direction in a firstsignal line layer, the metal line along the first direction beingconnected to the plurality of metal blocks through vias, respectively.9. The display panel of claim 8, wherein a respective metal block of theplurality of metal blocks has a L shape; an orthographic projection of afirst channel part of the active layer of the third transistor on thebase substrate overlaps with an orthographic projection of a first metalportion of the respective metal block of the plurality of metal blockson the base substrate; an orthographic projection of a second channelpart of the active layer of the third transistor on the base substrateoverlaps with an orthographic projection of a second metal portion ofthe respective metal block of the plurality of metal blocks on the basesubstrate; and the first metal portion and the second metal portion area first gate electrode and a second gate electrode of the thirdtransistor.
 10. The display panel of claim 1, further comprising: aplurality of first reset signal lines respectively along a firstdirection in a semiconductor material layer; and a plurality of secondreset signal lines respectively along a second direction in a secondsignal line layer; wherein the plurality of first reset signal linesrespectively cross over the plurality of second reset signal lines; arespective one of the plurality of first reset signal lines is connectedto at least multiple ones of the plurality of second reset signal linesthrough vias; and a respective one of the plurality of second resetsignal lines is connected to at least multiple ones of the plurality offirst reset signal lines through vias.
 11. The display panel of claim 1,further comprising a plurality of second low voltage signal linesrespectively along a second direction in a second signal line layer;wherein the plurality of second low voltage signal lines areelectrically connected to a cathode of a light emitting element.
 12. Thedisplay panel of claim 1, further comprising: a plurality of first highvoltage signal lines respectively extending along the first direction ina first signal line layer; and a plurality of second high voltage signallines respectively extending along a second direction in a second signalline layer; wherein the plurality of first high voltage signal linesrespectively cross over the plurality of second high voltage signallines; a respective one of the plurality of first high voltage signallines is connected to at least multiple ones of the plurality of secondhigh voltage signal lines through vias; and a respective one of theplurality of second high voltage signal lines is connected to at leastmultiple ones of the plurality of first high voltage signal linesthrough vias.
 13. The display panel of claim 12, wherein a respectiveone of the plurality of first high voltage signal lines comprises: amain body extending along a first direction; a protrusion protrudingaway from the main body along a second direction, and wherein theprotrusion is a portion where the respective one of the plurality ofsecond high voltage signal line is connected to a respective one of theplurality of first high voltage signal lines through one or more vias.14. The display panel of claim 12, wherein the respective pixel drivingcircuit further comprises a driving transistor, and a node connectingline connecting a drain electrode of the third transistor with a gateelectrode of the driving transistor; wherein the drain electrode of thethird transistor is connected to the gate electrode of the drivingtransistor; a source electrode of the third transistor is connected to adrain electrode of the driving transistor; and an orthographicprojection of the respective one of the plurality of second high voltagesignal lines on the base substrate covers an orthographic projection ofthe node connecting line on the base substrate.
 15. The display panel ofclaim 12, wherein an orthographic projection of the respective one ofthe plurality of second high voltage signal lines on the base substrateat least partially overlaps with an orthographic projection of at leastone gate electrode of the third transistor on the base substrate. 16.The display panel of claim 1, wherein the display panel comprises: aplurality of light emitting elements; and an interconnected firstvoltage supply network configured to provide a first voltage signal tocathodes of the plurality of light emitting elements; wherein theinterconnected first voltage supply network comprises signal lines in adisplay area of the display panel, the display area being at leastpartially surrounded by a peripheral area; the signal lines comprise aplurality of first signal lines in a first signal line layer and aplurality of second signal lines in a second signal line layer; thedisplay panel further comprises a planarization layer between the firstsignal line layer and the second signal line layer; and the plurality offirst signal lines are electrically connected to the plurality of secondsignal lines.
 17. The display panel of claim 16, wherein theinterconnected first voltage supply network comprises: a plurality offirst-first voltage signal lines respectively along a first direction;and a plurality of second-first voltage signal lines respectively alonga second direction; wherein the plurality of first-first voltage signallines respectively cross over the plurality of second-first voltagesignal lines.
 18. The display panel of claim 17, wherein theinterconnected first voltage supply network comprises a firstsub-network formed by the plurality of first-first voltage signal linesand a second sub-network formed by the plurality of second-first voltagesignal lines.
 19. The display panel of claim 17, wherein a respectiveone of the plurality of first-first voltage signal lines is connected toat least multiple ones of the plurality of second-first voltage signallines; and a respective one of the plurality of second-first voltagesignal lines is connected to at least multiple ones of the plurality offirst-first voltage signal lines.
 20. The display panel of claim 17,wherein the plurality of first-first voltage signal lines and theplurality of second-first voltage signal lines interconnect throughfirst vias respectively extending through the planarization layer, atleast some of the first vias being in the display area; a respective oneof the plurality of first-first voltage signal lines is connected to atleast multiple ones of the plurality of second-first voltage signallines respectively through multiple first vias extending through theplanarization layer; and a respective one of the plurality ofsecond-first voltage signal lines is connected to at least multiple onesof the plurality of first-first voltage signal lines respectivelythrough multiple first vias extending through the planarization layer.